Physical Design

Floorplan → place → CTS → route → sign-off. The netlist-to-GDSII flow: floorplanning and power planning, placement, clock-tree synthesis, routing, and sign-off checks for IR drop, electromigration, crosstalk and antenna.

• Physical Design — Turning a netlist into manufacturable layout. Learn floorplanning, power planning and IR drop, placement and utilisation, clock-tree synthesis, routing and congestion, wire delay (Elmore), parasitic extraction, physical verification (DRC, LVS, antenna), yield and dies per wafer.
• Floorplanning & Power Planning — The first physical-design step decides the chip's shape and the fate of everything after it. Learn die and core sizing, utilization and aspect ratio, IO ring and pad placement, macro placement rules, blockages and halos, power-grid design (rings, straps, rails), voltage areas, and how floorplan quality drives timing, congestion and IR drop.
• Placement & Optimisation — Placement decides the exact location of millions of standard cells. Learn wirelength (HPWL) as the objective, global placement (analytical and annealing), legalization and detailed placement, timing-driven and congestion-driven placement, density, and placement-time optimisation (buffering, sizing, cloning, Vt swaps) — with a working simulated-annealing placer in Python.
• Clock-Tree Synthesis (CTS) — The clock reaches every flip-flop on the chip. Learn clock-tree goals (skew, latency, transition, power), H-trees, buffered trees and meshes, skew and its effect on setup and hold, useful skew, clock gating in the tree, non-default routing rules, OCV/CRPR, and how to compute tree depth and timing windows.
• Routing: Global, Track & Detailed — Routing turns connections into real metal wires and vias on up to 15+ layers. Learn metal stacks and preferred directions, global routing and congestion, track assignment, detailed routing with maze (Lee) and A* search, design rules, vias and double patterning, timing- and SI-driven routing, and a working Lee router in Python.
• Sign-off: IR Drop, EM, Crosstalk & Antenna — Before tape-out a chip must pass every sign-off check. Learn static and dynamic IR drop, electromigration (EM) and Black's equation, crosstalk delay and glitch, antenna effect, multi-corner multi-mode (MCMM) STA, ECOs, the final checklist (STA, LEC, DRC, LVS, IR/EM, SI) and GDSII tape-out — with an IR-drop calculator for a power rail.