Layout, DRC, LVS & Parasitic Extraction

Before tape-out, the layout must be manufacturable and must match the schematic. Learn layers and stick diagrams, standard-cell layout, design rules and DRC, layout-versus-schematic (LVS), antenna and density checks, parasitic extraction (R and C of wires), wire RC delay, and how sign-off tools (Calibre, Pegasus, KLayout, Magic) are used.

Layout is the drawing that becomes the masks: polygons on layers such as diffusion, poly, contacts and metals. A single rule violation — two metal lines 1 nm too close — can short the chip, so every polygon is checked automatically.

Physical verification answers three questions: can the fab build it (DRC), is it the circuit we designed (LVS), and how do real wires slow and couple it (extraction)? Only when all three are clean is a design 'taped out'.

An analogy

DRC is a building inspector checking wall thickness and door widths against the code; LVS checks the built house against the architect's plan, room by room; extraction measures how long the real plumbing is so you know how fast water arrives.

Layout layers and stick diagrams

A transistor forms where poly crosses diffusion. Contacts connect diffusion/poly to metal1; vias connect metal layers. Stick diagrams sketch topology with coloured lines before drawing real polygons; standard cells use fixed-height rows with shared VDD/VSS rails at top and bottom.

DRC — design rule checking

Rules come from the fab's process limits:

LVS — layout versus schematic

LVS extracts devices and connectivity from the layout and compares them with the netlist: device counts, sizes and every connection. Typical errors are shorts (two nets merged), opens (a net split), missing devices and wrong sizes. LVS clean means the layout is electrically the circuit you simulated.

Parasitic extraction and signoff

Extraction (StarRC, Quantus, OpenRCX) computes wire resistances and ground/coupling capacitances, writing SPEF/DSPF files. Timing, power, IR-drop and noise signoff all use these parasitics — so extraction accuracy directly decides whether silicon meets frequency. Antenna rules prevent charge collected on long metal during plasma etch from damaging thin gate oxides (fixed with diodes or layer jumps).

Formulas

Worked example: Counting squares

Given: M1 wire 200 µm long, 0.1 µm wide, R_□ = 0.08 Ω

Find: R.

Answer: 160 Ω

Worked example: Wire delay

Given: 1 mm wire, R = 800 Ω, C = 200 fF

Find: t₅₀.

Answer: ≈ 60.8 ps

Worked example: LVS error diagnosis

Given: LVS reports net 'VDD' and net 'OUT' merged

Find: Cause.

Answer: Short between VDD and OUT — fix the overlapping polygon

RC delay of an on-chip wire grows with length squared

# RC of an on-chip copper wire (distributed line)
Rs = 0.08          # sheet resistance, ohm/square
c_per_um = 0.2e-15 # capacitance per um, F
W = 0.1            # width, um

for L in (100, 1000, 5000):          # length, um
    R = Rs * L / W
    C = c_per_um * L
    t50 = 0.38 * R * C               # 50 % delay of a distributed RC line
    print(f"L={L:5d} um: R={R:7.0f} ohm  C={C*1e15:6.0f} fF  delay={t50*1e12:8.1f} ps")
# L=  100 um: R=     80 ohm  C=    20 fF  delay=     0.6 ps
# L= 1000 um: R=    800 ohm  C=   200 fF  delay=    60.8 ps
# L= 5000 um: R=   4000 ohm  C=  1000 fF  delay=  1520.0 ps

5× longer wire → 25× more delay. That is why long nets get repeaters (buffers) inserted — splitting a wire into k segments makes delay grow linearly instead of quadratically.

A DRC rule deck fragment (KLayout Ruby DRC)

metal1 = input(34, 0)          # layer/datatype of M1
via1   = input(35, 0)

metal1.width(0.06.um).output("M1.W.1", "M1 width < 60 nm")
metal1.space(0.06.um).output("M1.S.1", "M1 spacing < 60 nm")
via1.not_inside(metal1).output("V1.EN.1", "Via1 not enclosed by M1")
metal1.with_area(0, 0.01.um2).output("M1.A.1", "M1 area too small")

Each rule is a geometric query on polygons; violations become markers you fix in the layout editor. Foundry decks contain thousands of such rules.

Common mistakes

Applications

Key takeaways

Going further