Digital IC Design

How digital chips are designed: specification, architecture, RTL, verification, synthesis, physical design and sign-off. Learn standard cells and libraries, design metrics (performance, power, area — PPA), gate-count and area estimation, clocking, low-power techniques and the front-end/back-end split.

A modern SoC contains billions of transistors designed by hundreds of engineers using automated EDA flows. Designers describe behaviour in RTL, and tools map it to standard cells, place them, route wires and verify timing and power.

An analogy

Designing a chip is like building a city: architects plan districts (blocks), builders use standard prefabricated houses (standard cells), and roads (wires) and utilities (power, clock) must reach everywhere on time.

Design flow

Specification → micro-architecture → RTL coding (Verilog/VHDL/SystemVerilog) → functional verification → logic synthesis → DFT insertion → floorplan, placement, clock tree, routing → static timing, power, physical verification (DRC/LVS) → tape-out.

Standard cells

Libraries contain characterised gates (NAND, NOR, flip-flops, MUXes) at several drive strengths and threshold voltages, with timing/power models (Liberty .lib) and layouts. Synthesis picks cells to meet constraints.

Clocking and power

Synchronous design with clock domains, clock gating to save power, multiple voltage islands, power gating for idle blocks, and careful clock-domain crossings.

Trade-offs

Pipelining raises frequency but adds latency and flops; parallelism raises throughput at area cost; lower voltage saves power but slows gates. SoCs integrate CPUs, GPUs, accelerators, memories and IP from third parties.

Formulas

• Area estimate: A ≈ (gates × 4 transistors / density) / utilisation
• Dynamic power: P = α C_total V² f
• Max frequency: f_max = 1 / (t_cq + t_logic + t_su + skew)

Worked example: Area estimate

Given: 10 M gate equivalents; 100 MTr/mm², utilisation 67 %

Find: Logic area.

• Transistors = 40 M
• Area = 0.4 mm² / 0.67 ≈ 0.6 mm²

Answer: ≈ 0.6 mm² (plus memories and I/O)

Worked example: Pipelining

Given: Logic 3.2 ns, t_cq + t_su = 0.3 ns

Find: f_max before and after a 2-stage split.

• Before: 3.5 ns → 286 MHz
• After: 1.6 + 0.3 = 1.9 ns → 526 MHz

Answer: ≈ 1.8× faster, one extra cycle of latency

Common mistakes

• Wrong: Late architectural changes. — Right: Fix architecture before RTL — changes cost exponentially more later.
• Wrong: Ignoring power until the end. — Right: Plan clock/power gating from architecture.

Applications

• Processors: CPUs, GPUs, NPUs.
• Networking: Switch and PHY ASICs.
• Consumer SoCs: Phones, TVs, wearables.

Key takeaways

• Spec → RTL → verify → synthesise → P&R → sign-off.
• Standard cells and libraries.
• Balance PPA.
• Pipelining vs parallelism.

Going further

• Chiplets: Multi-die packaging with UCIe.
• Power intent (UPF): Voltage domains and isolation.
• High-level synthesis: C++ to RTL.