The CMOS Inverter: VTC, Noise Margins, Delay & Power

The inverter is the atom of digital CMOS. Learn its operation, the voltage-transfer characteristic (VTC), switching threshold and PMOS/NMOS sizing, noise margins, propagation delay from R·C, rise/fall times, fan-out, and the three kinds of power — dynamic, short-circuit and leakage. Every other gate is analysed the same way.

A CMOS inverter is just one PMOS (pull-up to VDD) and one NMOS (pull-down to ground) with joined gates and joined drains. When the input is low the PMOS conducts and the output is VDD; when high, the NMOS conducts and the output is 0. In either steady state one transistor is off, so almost no current flows — the reason CMOS won.

Delay, power and noise immunity of billions of gates follow from the same few equations you learn here: the switching threshold, the RC time constant of the driving transistor and the load, and αCV²f.

An analogy

Picture a seesaw with a spring to the ceiling (PMOS) and a spring to the floor (NMOS). The input decides which spring is engaged. If both springs are equally strong, the seesaw flips exactly at the midpoint; make one stronger and the flip point shifts.

How it switches

Input 0: NMOS off, PMOS on → output pulled to VDD. Input 1: PMOS off, NMOS on → output pulled to 0. The output is a full rail-to-rail swing (V_OH = VDD, V_OL = 0) and there is no static path from VDD to ground.

VTC, V_M and noise margins

Sweeping V_in traces an S-shaped curve. V_M is where it crosses V_out = V_in. V_IL and V_IH are the points where the slope is −1; inputs between them are 'undefined'. Noise margins tell you how much noise a signal can pick up and still be read correctly. Equal-strength devices (PMOS ≈ 2–3× wider, since holes are slower) put V_M near VDD/2 and balance the margins.

Delay

Switching charges or discharges C_L through the on-transistor, like an RC circuit: t_p ≈ 0.69·R·C. To go faster: reduce C_L (smaller fan-out, shorter wires), reduce R (wider transistors, higher VDD), or both. Wider transistors also load the previous stage — the trade-off logical effort optimises.

Power components

Dynamic power αCV²f dominates in active logic — quadratic in V_DD, which is why voltage scaling is so effective. Short-circuit power flows briefly while both transistors conduct during slow input edges (keep rise times comparable to output). Leakage (subthreshold, gate, junction) flows all the time and grows as V_t shrinks — managed with multi-V_t libraries and power gating.

Formulas

• Switching threshold: V_M = (V_tn + r(V_DD − |V_tp|)) / (1 + r), r = √(k_p/k_n)
• Noise margins: NM_H = V_OH − V_IH, NM_L = V_IL − V_OL
• Propagation delay: t_p ≈ 0.69 · R_eff · C_L, t_p = (t_pHL + t_pLH)/2
• Symmetric sizing: (W/L)_p ≈ (μₙ/μₚ)·(W/L)_n ≈ 2–3×
• Dynamic power: P_dyn = α · C_L · V_DD² · f
• Energy per transition: E = ½ C_L V_DD² (dissipated); C_L V_DD² drawn per 0→1→0 cycle
• Leakage power: P_leak = V_DD · I_off

Worked example: Switching threshold

Given: V_DD = 1.2 V, V_tn = |V_tp| = 0.4 V, k_p = k_n

Find: V_M.

• r = 1
• V_M = (0.4 + 1 × 0.8) / 2

Answer: V_M = 0.6 V = V_DD/2

Worked example: Propagation delay

Given: R_eff = 5 kΩ, C_L = 10 fF

Find: t_p.

• t_p = 0.69 × 5 kΩ × 10 fF

Answer: 34.5 ps

Worked example: Dynamic power

Given: Chip: switched C = 1 nF total, α = 0.1, V_DD = 1.0 V, f = 1 GHz

Find: P_dyn.

• 0.1 × 1 nF × 1² × 1 GHz

Answer: 0.1 W

SPICE: transient and DC analysis of an inverter

* CMOS inverter characterisation
.include models.lib
VDD vdd 0 DC 1.0
VIN in  0 PULSE(0 1.0 100p 20p 20p 480p 1n)
MP  out in vdd vdd pmos W=0.4u L=50n     ; ~2x wider than NMOS
MN  out in 0   0   nmos W=0.2u L=50n
CL  out 0 5f                             ; fan-out + wire load

.dc  VIN 0 1.0 0.005                     ; voltage-transfer characteristic
.tran 1p 2n                              ; delay measurement
.measure tran tpHL TRIG V(in) VAL=0.5 RISE=1 TARG V(out) VAL=0.5 FALL=1
.measure tran tpLH TRIG V(in) VAL=0.5 FALL=1 TARG V(out) VAL=0.5 RISE=1
.end

The .dc sweep gives the VTC (V_M and noise margins); the .measure statements report propagation delays directly. This is how standard-cell libraries are characterised — thousands of such runs per cell.

Common mistakes

• Wrong: Sizing PMOS equal to NMOS and expecting symmetric delays. — Right: Holes are ~2–3× slower; widen the PMOS.
• Wrong: Thinking CMOS uses no power. — Right: Static power is small, but dynamic and leakage power are not.
• Wrong: Ignoring slow input edges. — Right: They increase short-circuit current and delay.

Applications

• Buffers & clock trees: Chains of inverters drive large loads quickly.
• Ring oscillators: Odd inverter rings measure process speed on every wafer.
• Level shifting: Skewed inverters shift thresholds between voltage domains.
• SRAM cells: Two cross-coupled inverters store each bit.

Key takeaways

• PMOS pulls up, NMOS pulls down; one is always off.
• Sizing sets V_M and delay symmetry.
• t_p ≈ 0.69RC; power ≈ αCV²f + V·I_off.
• Voltage is the strongest knob for power.

Going further

• Near-threshold computing: Operating near V_t for extreme energy efficiency.
• Stacking effect: Two series off-transistors leak much less than one.
• Miller effect: Gate–drain capacitance doubles its effect during switching.