SystemVerilog & Verification

Verification takes more than half of chip-design effort. Learn SystemVerilog design enhancements (logic, always_ff/always_comb, interfaces, structs), verification features (classes, constrained-random stimulus, functional coverage, assertions/SVA), UVM testbench architecture, and formal verification basics.

A single bug found after tape-out can cost millions and months. SystemVerilog adds object-oriented testbenches, randomisation, coverage and assertions so engineers can explore enormous state spaces automatically.

An analogy

Verification is like crash-testing a car in a simulator thousands of times with random conditions, checking every sensor (assertions) and making sure every scenario was tried (coverage).

Design improvements

logic replaces wire/reg confusion; always_ff, always_comb and always_latch state intent (tools warn on mismatches); enums, structs, packages and interfaces make RTL cleaner and less error-prone.

Constrained-random and coverage

Instead of hand-writing every test, randomise transactions within constraints, check results with a scoreboard/reference model, and use functional coverage to know when enough has been tested.

Assertions

Immediate assertions check conditions in procedural code; concurrent assertions (SVA) describe temporal behaviour across cycles. They catch bugs at the source and document intent.

UVM and formal

UVM structures testbenches into agents (driver, monitor, sequencer), environments, scoreboards and sequences for reuse. Formal verification mathematically proves properties for all inputs — ideal for control logic, arbiters and security.

Formulas

• Coverage: Coverage % = bins hit / total bins × 100
• Assertion (implication): req |-> ##[1:3] ack (ack within 1–3 cycles after req)

Worked example: Coverage closure

Given: Cross coverage of 4 opcodes × 8 address regions = 32 bins; 28 bins hit

Find: Coverage.

• 28/32 = 87.5 %

Answer: 87.5 % — write directed/biased tests for the 4 missing bins

Worked example: Assertion meaning

Given: req |-> ##[1:3] ack

Find: Interpretation.

• Whenever req is high at a clock edge, ack must be high 1, 2 or 3 cycles later

Answer: Checks handshake latency automatically

Constrained-random transaction, coverage and assertion

class bus_txn;
  rand bit [7:0]  addr;
  rand bit [31:0] data;
  rand bit        write;
  constraint c_addr { addr inside {[8'h00:8'h3F]}; }      // legal register space
  constraint c_mix  { write dist {1 := 70, 0 := 30}; }     // 70 % writes
endclass

module tb;
  logic clk = 0, req, ack;
  always #5 clk = ~clk;

  covergroup cg @(posedge clk);
    coverpoint req;
    coverpoint ack;
    cross req, ack;
  endgroup
  cg cov = new();

  // ack must arrive 1 to 3 cycles after every request
  property p_handshake;
    @(posedge clk) req |-> ##[1:3] ack;
  endproperty
  assert property (p_handshake) else $error("ack timeout");

  initial begin
    bus_txn t = new();
    repeat (100) begin
      assert (t.randomize());
      $display("addr=%h data=%h write=%0b", t.addr, t.data, t.write);
    end
  end
endmodule

Constraints keep random stimulus legal while exploring corner cases; covergroups measure which scenarios were exercised; assertions check protocol rules every cycle automatically.

Common mistakes

• Wrong: Code coverage = verification complete. — Right: Also measure functional coverage and check results.
• Wrong: Over-constraining random stimulus. — Right: Leave room to hit unexpected corner cases.

Applications

• SoC verification: UVM environments for IP blocks.
• Protocol checking: SVA for AXI, PCIe, USB.
• Formal sign-off: Proving control and security properties.

Key takeaways

• SV adds cleaner RTL constructs.
• Constrained random + coverage + scoreboard.
• Assertions check temporal rules.
• UVM and formal scale verification.

Going further

• UVM RAL: Register abstraction layer.
• Emulation: Hardware-accelerated verification.
• Portable Stimulus: Scenario reuse across platforms.