8085 Microprocessor

The Intel 8085 is the classic 8-bit teaching processor. Learn its architecture (accumulator, registers B–L, flags, SP, PC), multiplexed address/data bus, pin functions, addressing modes, instruction groups, T-states and machine cycles, assembly programming and software delay loops.

Introduced in 1976, the 8085 has an 8-bit data bus and 16-bit address bus (64 KB). Its simple, transparent design makes it ideal for learning how instructions, buses and timing really work — concepts that carry over to every modern processor.

An analogy

The 8085 is like a manual car: everything is visible and controlled by you, which is why it's great for learning to drive before switching to an automatic.

Architecture

8-bit ALU with accumulator, six general registers usable as pairs, 16-bit SP and PC, flag register. Internal clock = crystal/2 (e.g. 6 MHz crystal → 3 MHz).

Bus and pins

AD0–AD7 carry the low address then data (demultiplexed with ALE and a 74LS373 latch); A8–A15 carry the high address. Control: RD, WR, IO/M, ALE; interrupts TRAP, RST 7.5/6.5/5.5, INTR; serial SID/SOD.

Instructions and addressing

Groups: data transfer (MOV, MVI, LDA, STA, LXI), arithmetic (ADD, SUB, INR, DCR), logical (ANA, ORA, XRA, CMP), branch (JMP, JZ, CALL, RET), machine control (HLT, NOP, EI, DI). Addressing modes: immediate, register, direct, register indirect, implied.

Timing

Each instruction = machine cycles (opcode fetch, memory read/write, I/O read/write), each = 3–6 T-states. Timing diagrams show ALE, RD/WR and bus contents per T-state — the basis for interfacing memory and peripherals.

Formulas

• Instruction time: t = T-states × (1/f_clk)
• Loop delay (MVI + DCR/JNZ): T_total = 7 + 14(N − 1) + 11
• Address space: 2¹⁶ = 64 KB

Worked example: Instruction time

Given: MVI (7 T-states), 3 MHz clock

Find: Time.

• t = 7 × 0.333 µs = 2.33 µs

Answer: 2.33 µs

Worked example: Delay loop

Given: MVI C, FFH; DCR C; JNZ; 3 MHz

Find: Delay.

• T = 7 + 14 × 254 + 11 = 3574
• t = 3574 × 0.333 µs = 1.19 ms

Answer: ≈ 1.19 ms

Add two numbers and delay loop (8085 assembly)

; Add the bytes at 2050H and 2051H, store sum at 2052H, carry at 2053H
        LXI  H, 2050H     ; HL -> first operand
        MOV  A, M         ; A = [2050H]
        INX  H
        ADD  M            ; A = A + [2051H]
        STA  2052H        ; store sum
        MVI  A, 00H
        ACI  00H          ; A = carry
        STA  2053H
        HLT

; Software delay: ~1.19 ms at 3 MHz
DELAY:  MVI  C, FFH       ; 7 T
LOOP:   DCR  C            ; 4 T
        JNZ  LOOP         ; 10 T (taken) / 7 T (not taken)
        RET

HL acts as a memory pointer (M = memory at HL). Delay loops count T-states: 7 + 14 × 254 + 11 = 3574 T ≈ 1.19 ms at a 3 MHz internal clock.

Common mistakes

• Wrong: Forgetting to demultiplex AD0–AD7. — Right: Latch the low address with ALE.
• Wrong: Using crystal frequency as the T-state clock. — Right: Internal clock = crystal/2.

Applications

• Education: Teaching assembly and bus timing.
• Legacy systems: Old industrial controllers.
• Foundation: Concepts reused in MCUs and x86.

Key takeaways

• 8-bit data, 16-bit address.
• Multiplexed AD0–AD7 with ALE.
• Instructions: transfer, arithmetic, logic, branch, control.
• Delays counted in T-states.

Going further

• 8255 PPI: Programmable parallel ports.
• 8259 PIC: Interrupt controller expansion.
• Timing diagrams: Memory read/write cycles.