Memory & Peripheral Interfacing

Connecting a processor to memory and I/O. Learn memory types (SRAM, DRAM, ROM, Flash, EEPROM), address decoding and memory maps, chip capacity and expansion, memory-mapped vs isolated I/O, wait states and access timing, programmable peripherals (8255, 8253/8254, 8251, 8259), and DMA.

A processor alone does nothing useful — it needs program memory, data memory and peripherals. Interfacing means wiring address, data and control lines so each device responds only at its assigned addresses, with timing the devices can meet.

An analogy

A memory map is like a street directory: each house (chip) has a range of addresses, and the address decoder is the postman delivering to the right door.

Memory types

ROM/Flash (non-volatile program storage), EEPROM (byte-writable non-volatile), SRAM (fast, static, no refresh — caches and MCU RAM), DRAM (dense, needs refresh — main memory, DDR). Memory is organised as words × bits (e.g. 8K × 8).

Address decoding

Lower address lines go to every chip; higher lines feed a decoder that asserts one chip select. Full decoding gives unique addresses; partial decoding saves logic but creates mirror images.

I/O interfacing

Memory-mapped I/O treats peripheral registers as memory (ARM, most MCUs). Isolated I/O uses separate IN/OUT instructions (8085/x86). Classic peripherals: 8255 parallel ports, 8254 timer, 8251 USART, 8259 interrupt controller, 8237 DMA.

Timing and DMA

If a device is slower than the bus cycle, insert wait states (READY line). DMA controllers move data between memory and peripherals without CPU involvement — essential for high data rates. Modern buses (AHB/AXI) add bursts and arbitration.

Formulas

• Chip capacity: Locations = 2^(address lines)
• Chips needed: N = required size / chip size
• Wait states: WS = ⌈(t_acc − t_available) / T_clk⌉
• Memory map range: End = Start + size − 1

Worked example: Memory expansion

Given: Need 64 KB RAM from 16 K × 8 chips

Find: Chips and address lines.

• N = 64/16 = 4 chips
• Each chip: 2¹⁴ = 16K → A0–A13; A14–A15 decoded to 4 chip selects

Answer: 4 chips, 2-to-4 decoder on A15–A14

Worked example: Wait states

Given: Flash t_acc = 70 ns; CPU allows 45 ns at 40 MHz (T = 25 ns)

Find: Wait states.

• (70 − 45)/25 = 1.0 → 1 wait state

Answer: 1 wait state

Common mistakes

• Wrong: Overlapping memory ranges. — Right: Draw a memory map and check decoding.
• Wrong: Ignoring access time. — Right: Add wait states or faster memory.

Applications

• Embedded boards: External SRAM/Flash on FMC buses.
• PC architecture: Memory maps and PCIe BARs.
• Industrial I/O: Parallel ports and counters.

Key takeaways

• Locations = 2^address lines.
• Decoders make chip selects.
• Memory-mapped vs isolated I/O.
• Wait states and DMA for timing and throughput.

Going further

• DDR interfacing: Training, termination and timing.
• AMBA AHB/AXI: On-chip bus protocols.
• MMU & MPU: Virtual memory and protection.