Blocking vs Non-Blocking Assignment

Why clocked blocks use <= and combinational blocks use =, shown by a shift register that collapses when you get it wrong.

Verilog has two assignment operators. Blocking (=) updates the variable immediately, so the next statement sees the new value. Non-blocking (<=) evaluates the right-hand side now but schedules the update for the end of the time step, so every statement in the block sees the old values. This difference decides how many flip-flops you get.

The two rules

always @(posedge clk) begin temp = a + b; sum = temp; end always @(posedge clk) sum <= a + b;

Blocking assignments in a clocked block make the result depend on statement order and can collapse registers. Compute combinational values outside, or use <= throughout.

always @(*) begin y <= a & b; // non-blocking in combinational logic end always @(*) begin y = a & b; end

Non-blocking in combinational blocks still simulates, but intermediate values chained through several statements are seen one delta step late. Use = for combinational logic.

How do you swap two registers on a clock edge?

always @(posedge clk) begin a <= b; b <= a; end — both right-hand sides are read before either update, so the values swap. With = the second line would read the already-updated a.

Can you assign the same reg from two different always blocks?

No (for synthesizable code). It creates multiple drivers: simulation results depend on block ordering and synthesis either errors out or builds something you did not intend.

always @(posedge clk) begin b = a; c = b; end — how many flip-flops does this create, and what is c after one clock?

c gets the new b, which is already a, so after one clock both b and c equal a: there is no two-stage delay. Synthesis builds flip-flops that all load a and usually merges them into one. With <= you would get a two-stage pipeline (c lags b by a clock).